pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x00 MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x70 MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x00 MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x70 + MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x00 /* CON8_29 */ + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x00 /* CON8_28 */ >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00 MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x70 MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00 MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x70 + MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00 /* CON8_77 */ + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00 /* CON8_76 */ >; }; pinctrl_uart4: uart4grp { fsl,pins = < MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x00 MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x70 MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x00 MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x70 + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x00 /* CON8_30 */ + MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x00 /* CON8_31 */ >; }; pinctrl_ext_hog_1: ext_hoggrp-1 { fsl,pins = < - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00 /* CON8_76 */ - MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00 /* CON8_77 */ MX7D_PAD_SD2_CMD__GPIO5_IO13 0x00 /* CON8_66 */ - MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x00 /* CON8_28 */ - MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x00 /* CON8_29 */ - MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x00 /* CON8_30 */ - MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x00 /* CON8_31 */ MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x00 /* CON8_32 */ MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x00 /* CON8_33 */ MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x00 /* CON8_34 */ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x00 /* CON8_35 */ MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x00 /* CON8_36 */ MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x00 /* CON8_37 */ MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x00 /* CON8_38 */ MX7D_PAD_ENET1_COL__GPIO7_IO15 0x00 /* CON8_39 */ >; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>, <&clks IMX7D_UART1_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; assigned-clock-rates = <0>, <80000000>; + /* DE端子をGPIOで制御するための設定 */ + rs485-rts-active-high; + rs485-enabled-at-boot-time; + rts-gpio = <&gpio7 5 0>; + fsl,uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>, <&clks IMX7D_UART2_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; assigned-clock-rates = <0>, <80000000>; + /* DE端子をGPIOで制御するための設定 */ + rs485-rts-active-high; + rs485-enabled-at-boot-time; + rts-gpio = <&gpio3 5 0>; + fsl,uart-has-rtscts; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>, <&clks IMX7D_UART4_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; assigned-clock-rates = <0>, <80000000>; + /* DE端子をGPIOで制御するための設定 */ + rs485-rts-active-high; + rs485-enabled-at-boot-time; + rts-gpio = <&gpio7 6 0>; + fsl,uart-has-rtscts; status = "okay"; }; +&gpio3 { + rs485_re_u2 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "RS485_RE_U2"; + }; +}; + +&gpio7 { + rs485_re_u1 { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "RS485_RE_U1"; + }; + + rs485_re_u4 { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "RS485_RE_U4"; + }; +};