/* * Copyright (C) 2018-2019 Atmark Techno, Inc. All Rights Reserved. * * SPDX-License-Identifier: (GPL-2.0 OR MIT) */ #include #include "armadillo-610-onboard-usdhc2.dtsi" &iomuxc_snvs { pinctrl_expansion_interfacehog_snvs: expansion_interfacehogsnvsgrp { fsl,pins = < /* CON2 */ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400010b0 // CON2_13 >; }; }; &iomuxc { pinctrl_expansion_interfacehog: expansion_interfacehoggrp { fsl,pins = < /* CON2*/ // CON2_1 USB1_DP // CON2_2 USB1_DN // CON2_3 GND // CON2_4 USB2_DN // CON2_5 USB2_DP // CON2_6 GND // CON2_7 USB1_VBUS // CON2_8 USB2_VBUS // CON2_9 ETHER_SPEEDLED // CON2_10 ETHER_LINK_ACTLED MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x400010b0 // CON2_11 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x400010b0 // CON2_12 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x400010b0 // CON2_14 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x400010b0 // CON2_17 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x400010b0 // CON2_18 MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x400010b0 // CON2_19 MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x400010b0 // CON2_20 MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x400010b0 // CON2_21 MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x400010b0 // CON2_22 MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x400010b0 // CON2_23 MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x400010b0 // CON2_24 MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x400010b0 // CON2_25 MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x400010b0 // CON2_26 MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x400010b0 // CON2_27 MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x400010b0 // CON2_28 MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x400010b0 // CON2_29 MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x400010b0 // CON2_30 MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x400010b0 // CON2_31 MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x400010b0 // CON2_32 MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x400010b0 // CON2_33 MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x400010b0 // CON2_34 MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x400010b0 // CON2_35 // CON2_36 GND MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x400010b0 // CON2_38 MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x400010b0 // CON2_39 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x400010b0 // CON2_41 // CON2_42 BJP1 MX6UL_PAD_JTAG_MOD__SJC_MOD 0x10b0 // CON2_43 //MX6UL_PAD_EXT_RESET_B__EXT_RESET_B 0x10b0 // CON2_44 // CON2_44 RESETBMCU // CON2_45 VCC_3.3V // CON2_46 VCC_3.3V // CON2_47 VIN // CON2_48 VIN // CON2_49 VIN // CON2_50 VIN // CON2_51 GND // CON2_52 GND // CON2_53 VCC_5V // CON2_54 VCC_5V MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x400010b0 // CON2_55 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x400010b0 // CON2_56 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x400010b0 // CON2_57 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x400010b0 // CON2_58 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x400010b0 // CON2_59 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x400010b0 // CON2_60 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400010b0 // CON2_61 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x400010b0 // CON2_62 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400010b0 // CON2_63 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x400010b0 // CON2_64 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400010b0 // CON2_65 MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x400010b0 // CON2_66 MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x400010b0 // CON2_67 MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x400010b0 // CON2_70 MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x400010b0 // CON2_71 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x400010b0 // CON2_72 MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x400010b0 // CON2_73 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x400010b0 // CON2_74 // CON2_75 GND MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x400010b0 // CON2_76 // CON2_77 PWRON // CON2_78 ONOFF // CON2_79 VDD_COIN_3V MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x400010b0 // CON2_80 MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x400010b0 // CON2_81 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x400010b0 // CON2_82 // CON2_83 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x400010b0 // CON2_84 // CON2_85 MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x400010b0 // CON2_86 MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x400010b0 // CON2_87 MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x400010b0 // CON2_88 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x400010b0 // CON2_89 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x400010b0 // CON2_90 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x400010b0 // CON2_91 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x400010b0 // CON2_92 // CON2_95 GND // CON2_96 ETHER_RXN // CON2_97 ETHER_RXP // CON2_98 GND // CON2_99 ETHER_TXN // CON2_100 ETHER_TXP >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x1b0b1 // CON2_15 MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x00008 // CON2_16 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 // CON2_68 MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x00008 // CON2_69 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 // CON2_93 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00008 // CON2_94 >; }; pinctrl_uart4: uart4grp { fsl,pins = < MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x00008 // CON2_37 MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 // CON2_40 >; }; pinctrl_uart5: uart5grp { fsl,pins = < MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x00008 // CON2_83 MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x1b0b1 // CON2_85 >; }; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; status = "okay"; }; / { regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; extreg_3v3: ext-regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; chosen { stdout-path = &uart1; }; aliases { }; };